60 practice questions
What does CPU clock speed measure?
easyExplain the purpose of the Program Counter (PC).
easyState the function of the Memory Address Register (MAR) and Memory Data Register (MDR).
mediumIn the fetch-execute cycle, what is the role of the Memory Address Register (MAR)?
easyWhich factor would most directly increase a CPU's ability to process more instructions per second, all else being equal?
mediumWhich of the following correctly lists the stages of the fetch-decode-execute cycle in order?
easyExplain what happens during the 'fetch' stage of the fetch-decode-execute cycle, naming the registers involved.
mediumWhich register holds the instruction currently being decoded by the CPU?
mediumExplain what happens during the 'decode' stage of the fetch-decode-execute cycle.
mediumDuring which stage of the fetch-decode-execute cycle is the Program Counter (PC) typically incremented (for a non-branching instruction)?
mediumName the three buses connecting CPU to memory and state each one's purpose.
mediumWhat is the effect of increasing the width of the data bus?
mediumWhat is the purpose of the accumulator register?
easyDescribe the role of the control unit within the CPU.
mediumState two ways cache memory improves CPU performance.
easyWhat is the difference between L1, L2 and L3 cache?
mediumWhat type of memory is cache?
easyExplain why a CPU with a larger cache might perform better than an otherwise identical CPU with a smaller cache.
mediumDescribe the role of the Arithmetic Logic Unit (ALU) within the CPU.
easyWhich CPU register holds the instruction that is currently being executed?
easyWhat is a von Neumann bottleneck?
hardExplain what is meant by "Von Neumann architecture" and identify one limitation of it.
mediumA key feature of Harvard architecture is that it:
mediumExplain why Harvard architecture is often used in embedded systems such as digital signal processors (DSPs).
mediumIn Von Neumann architecture, program instructions and data are stored:
easyCompare Von Neumann and Harvard architecture in terms of the 'von Neumann bottleneck'.
mediumWhich architecture is used by most general-purpose computers, such as desktop PCs and laptops?
easyExplain why Harvard architecture allows a CPU to fetch the next instruction and access data in memory at the same time.
hardHarvard architecture is commonly found in which type of system?
mediumExplain what is meant by a 'modified Harvard architecture' and why many modern CPUs use one.
hardExplain the difference between CISC and RISC with one advantage of each.
hardWhat is the purpose of an FPGA (Field-Programmable Gate Array)?
hardDescribe one advantage and one disadvantage of using a CISC processor compared to a RISC processor.
hardA typical feature of a RISC (Reduced Instruction Set Computer) processor is:
mediumExplain why RISC processors typically use a 'load-store' architecture.
mediumWhich well-known processor family is a classic example of a CISC (Complex Instruction Set Computer) architecture?
easyExplain a trade-off between using a RISC processor (simpler hardware, more instructions per program) and a CISC processor (more complex hardware, fewer instructions per program).
mediumWhich type of processor architecture (RISC or CISC) is most commonly used in smartphones and tablets, largely due to its lower power consumption?
easyExplain how the design of RISC processors makes pipelining easier to implement effectively.
mediumCompared to RISC instructions, CISC instructions often:
mediumExplain pipelining and describe one hazard that can disrupt it.
hardWhat is superscalar processing?
hardExplain how pipelining improves CPU performance, and identify one factor that can reduce its effectiveness.
hardA 'structural hazard' in a pipelined CPU occurs when:
mediumExplain what is meant by a 'data hazard' in a pipelined CPU, giving an example.
mediumA 'control hazard' in a pipelined CPU is most often caused by:
mediumExplain how branch prediction can help reduce the impact of control hazards in a pipelined CPU.
hardThe main benefit of pipelining in a CPU is that it:
easyExplain what a 'structural hazard' is in a pipelined CPU and describe one way it can be resolved.
mediumWhat is the purpose of a 'pipeline stall' (bubble)?
mediumWhat is the difference between a physical core and a logical core?
hardExplain the difference between a multi-core processor and a processor that uses hyper-threading.
hardA GPU is particularly well suited to which type of task?
mediumWhich of the following best describes "parallel processing"?
easyCompared to a typical CPU, a GPU (Graphics Processing Unit) generally has:
easyExplain what SIMD (Single Instruction, Multiple Data) means and why it makes GPUs well suited to certain tasks.
mediumA GPU is best suited to tasks that:
mediumExplain why training a neural network is often carried out using a GPU rather than a CPU.
mediumWhich statement best compares the number of cores in a typical modern CPU and GPU?
easyExplain why a GPU is not generally suitable as a replacement for a CPU for general-purpose, everyday tasks (e.g. running an operating system).
hardThe processor (CPU) fetches, decodes and executes instructions. The Control Unit (CU) coordinates and synchronises every operation, decodes instructions and manages the flow of data along the buses. The Arithmetic Logic Unit (ALU) performs all arithmetic (add, subtract, shift) and logic (AND, OR, comparisons). Registers are tiny, extremely fast storage locations inside the CPU. The clock generates regular pulses that synchronise operations — one or more pulses per stage.
| Register | Full name | Role |
|---|---|---|
| PC | Program Counter | Holds the address of the NEXT instruction to fetch |
| MAR | Memory Address Register | Holds the address currently being read from / written to |
| MDR | Memory Data Register | Holds the data/instruction just fetched, or about to be written |
| CIR | Current Instruction Register | Holds the instruction now being decoded and executed |
| ACC | Accumulator | Holds the working result of ALU operations |
| Bus | Direction | Carries | Width affects |
|---|---|---|---|
| Data bus | Bidirectional | Data and instructions between CPU and memory | Amount of data moved per transfer |
| Address bus | Unidirectional (CPU → memory) | The memory address to access | Maximum addressable memory (2^width) |
| Control bus | Bidirectional | Control/timing signals (read, write, clock, interrupt) | Coordination of components |
[PC] → MAR ; address of next instruction to MAR [MAR] → address bus memory[MAR] → data bus → MDR ; instruction fetched [MDR] → CIR ; instruction moved to CIR [PC] + 1 → PC ; PC incremented --- DECODE --- CU decodes the opcode in CIR, splits opcode/operand --- EXECUTE --- ALU performs the operation, result → ACC (or data moved, or [operand] → PC for a branch) --- then check the interrupt register and repeat ---
Von Neumann: a single memory and single bus shared by instructions AND data. Simpler and cheaper, but the shared bus is the "von Neumann bottleneck" — the CPU cannot fetch an instruction and read/write data at the same time. Harvard: physically separate memories and buses for instructions and data, so both can be accessed simultaneously — faster, and used where speed is critical (embedded systems, DSPs). Many modern CPUs are a hybrid: von Neumann main memory but separate L1 instruction and data caches (a Harvard-style split).
| Performance factor | Why it helps | Limit / trade-off |
|---|---|---|
| Clock speed | More FDE cycles per second | Heat and power rise sharply; physical limits |
| Number of cores | Several instruction streams run in parallel | Only helps tasks that can be parallelised |
| Cache size / levels | Fewer slow trips to main memory | Expensive; diminishing returns |
| Word length / bus width | More data moved/processed per cycle | More complex, costly hardware |
| Feature | CISC | RISC |
|---|---|---|
| Instruction set | Large, complex, variable length | Small, simple, fixed length |
| Cycles per instruction | Several (one instruction = much work) | Usually one |
| Program size | Shorter (complex instructions) | Longer (more simple instructions) |
| Hardware/compiler | Complex hardware; simpler compiler | Simple hardware; compiler does more work |
| Pipelining | Harder (variable-length instructions) | Easier (uniform instructions) |
| Power use | Higher | Lower — suits battery devices |
| Typical use | Desktop/server (x86) | Mobile, embedded (ARM) |
| Architecture | Meaning | Example |
|---|---|---|
| SISD | Single Instruction Single Data | Classic single-core CPU |
| SIMD | Single Instruction Multiple Data | GPU; vector operations on arrays |
| MISD | Multiple Instruction Single Data | Rare — fault-tolerant systems |
| MIMD | Multiple Instruction Multiple Data | Multicore CPU; cluster of computers |
A high clock speed with few powerful cores suits inherently sequential, single-threaded tasks. A GPU (SIMD) wins when the same calculation is applied to huge amounts of independent data. A multicore CPU (MIMD) wins for several different concurrent tasks/threads.
Justify a device choice against the scenario using: capacity, speed (access time / transfer rate), portability, durability (moving parts?), reliability, power consumption and cost per GB. E.g. a laptop OS drive → SSD (fast, shock-resistant, low power); a large cold backup → magnetic HDD (cheap per GB).
| Storage type | How it works | Pros | Cons |
|---|---|---|---|
| Magnetic (HDD) | Read/write head over spinning magnetised platters | Very cheap per GB, high capacity | Slow, fragile moving parts, noisy |
| Solid state (SSD/flash) | Charge stored in NAND flash cells, no moving parts | Fast, silent, shock-resistant, low power | Dearer per GB; finite write/erase cycles |
| Optical (CD/DVD/Blu-ray) | Laser reads pits and lands on a reflective layer | Cheap, removable, good for archival/distribution | Low capacity, slow, scratch-prone |
When physical RAM is too small for the active workload, the OS constantly swaps pages between RAM and disk. Because disk is far slower than RAM, the CPU spends most of its time waiting for paging rather than doing useful work — performance collapses. The fix is more RAM or fewer concurrent programs.